Phase locked loops (“PLL”) have been used extensively in analog electrical systems and communication systems. In today's high performance systems operating within increasingly stringent timing constraints, PLLs are being introduced in more general digital electronic circuits. For example, application specific integrated circuits (“ASIC”) used in a variety of circuit applications typically include on-chip PLLs for clock signal distribution.
The key advantages that PLLs bring to clock distribution are phase/delay compensation, frequency multiplication and duty cycle correction. A PLL enables one periodic signal or clock to be phase-aligned to frequency multiples of a reference clock. As the name implies, the output of the PLL locks onto the incoming reference clock signal and generates a periodic output signal with a frequency equal to the average frequency of the reference clock. When the output PLL signal tracks the reference signal, the PLL is said to be “locked.”
A PLL, however, will only remain locked over a limited frequency range or shift in frequency called a hold-in or lock range. The PLL generally tracks the reference signal over the lock range, provided the reference frequency changes slowly. This maximum “locked sweep rate” is the maximum rate of change of the reference frequency for which the PLL will remain locked. If the frequency changes faster than this rate, the PLL will drop out of lock.
Other factors may cause loss of lock that may occur unexpectedly and suddenly. For example, a power supply voltage variation may result in a deviation in the output frequency of the PLL. A deviation in the output frequency may cause a PLL to drop out of lock. An example of a power supply variation that could cause a PLL to drop out of lock is an increased load on the power supply. The increase load may be introduced by an increased number of circuit components that are sharing the power supply.
Power supply variations may also create other nuisances, one such nuisance being the variation in output frequency itself. The PLL may still remain “locked”, but a variable output frequency may cause instabilities in circuits referencing the PLL output.
A contributor to power supply variation is the voltage received by a voltage controlled oscillator (VCO) within a PLL. The function of the VCO is to generate the periodic output signal of the PLL. When a reference clock is being tracked by the PLL, a phase detector, along with other components, generates a voltage (or a current) representative of the phase difference between the reference clock and the output of the PLL. Basically, a VCO receives the generated voltage (or current) and translates it into the periodic output signal. For example, a high input voltage may be translated into an output signal with a fast frequency. A low input voltage, on the other hand, may be translated into an output signal with a low frequency.
If, however, power supply varies, the VCO may translate an input voltage into a range of periodic signals. That is, the periodic signal will vary as power supply varies. As a result, detrimental circuit errors that result from a deviation in PLL output or from a loss of lock in the PLL may occur. Therefore, there is a need for a power supply compensated voltage and current supply for a voltage controlled oscillator.